Micron skips a generation with plans for 400-layer flash memory in late 2027

Micron revealed during an October technology webinar that its next flash architecture will be G11, bypassing G10 entirely. Scheduled for mass production in the second half of 2027, the new node features over 400 layers and is designed to double bit density compared to current G9 memory, according to company presentations. [1][2]

The G11 design adopts wafer-on-wafer bonding, pairing a memory array wafer with a separate logic wafer to scale vertical layers without monolithic manufacturing penalties. Micron claims the technology delivers up to 1.5 times faster I/O speeds and cuts data-transfer energy per bit by over 25 percent. The roadmap also outlines future data-center solid-state drives reaching capacities up to 512TB, along with dedicated AI tiers that include high-IOPS single-level cell designs and high-bandwidth, through-silicon via stacked dies. [1]

The memory maker frames the architectural jump as a crucial supply lever as artificial intelligence infrastructure strains existing manufacturing capacity. Micron leadership warned that memory and storage markets will face prolonged shortages through 2027 and 2028, meaning dense architectures like G11 will be vital to keeping pace with surging enterprise data center demand. [1]