Reported by 3 outlets

Google expands eighth-generation artificial intelligence hardware with specialized TPU 8tx and 8i Max processors

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Google LLC has introduced two new specialized artificial intelligence chips, the TPU 8tx and TPU 8i Max, expanding its eighth-generation Tensor Processing Unit lineup. The additions build on the TPU 8t, designed for large-scale training, and the TPU 8i, built for real-time reasoning, which Google originally unveiled at Google Cloud Next 2026 in April. [2][3]

The new processors are tailored to handle agentic workloads while tackling hardware bottlenecks. The TPU 8tx is targeted at confidential inference and small-scale training tasks and pairs with custom AMD EPYC host processors. Meanwhile, the TPU 8i Max combines two TPU 8i chips into a single package to increase compute and memory density, an architecture aimed directly at resolving the memory wall challenge. [2][3]

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3 outlets
SiliconANGLE
[3] SiliconANGLE

Google advances agentic AI custom silicon expanding TPU family with 8tx and 8i Max

Google LLC today introduced two new specialized silicon chips for artificial intelligence to its eighth-generation Tensor Processing Unit architecture family, aimed at higher compute density and secure inference. At Google Cloud Next 2026 in April, Google introduced two specialized TPUs in the same generation, 8t for large-scale training and 8i designed for real-time reasoning. At the time,…

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Wccftech
[2] Wccftech

Google Pairs Its New TPU 8tx With Custom AMD EPYC CPU Hosts, While The TPU 8i Max Combines Two TPU 8i Chips In A Single Package To Offer Phenomenal Compute And Memory Density

Google has just expanded its TPU v8 family by introducing two new variants for agentic workloads, unlocking confidential inference and small-scale training with the TPU 8tx, while the TPU 8i Max attempts to solve the memory wall problem. An overview of Google's TPU 8t and TPU 8i chips Google's TPU 8t is housed within the "Zebra package" that physically integrates a central Logic chiplet, a dedicated SerDes chiplet, and multiple high-bandwidth memory stacks.

via Wccftech
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