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AMD has introduced its 6th Gen EPYC server line, codenamed Venice, marking the debut of its Zen 6 architecture built on TSMC 2 nm process technology. The new server chips scale up to 256 cores and 512 threads per socket, backed by 16 channels of DDR5 memory and native PCIe Gen 6 connectivity. Platforms using the SP7 package are shipping now, with Microsoft Azure previewing its HDv2 instances as the initial cloud offering. [1][2]
The release revamps AMD's chiplet design, increasing standard Zen 6 compute dies to 12 performance cores sharing 48 MB of L3 cache, while compact Zen 6c dies expand to 32 cores and 128 MB of L3 cache. Architectural updates add split integer schedulers and native FP16 support within a 512-bit vector engine. [1][2]
AMD claims a 20% IPC gain over Zen 5 in enterprise workloads and 31% in AI tasks. In early testing by Tom's Hardware, a dual-socket 256-core EPYC 9996 delivered a 93% throughput gain over a dual EPYC 9965 server in SPEC CPU 2026 integer benchmarks. AMD positions the platform against Nvidia's Vera, while future Venice-X, Verano, and consumer desktop processors are set to follow through 2027. [1][2]
AMD's new Zen 6 architecture is more than a routine refresh, with a 12-core CCD, 4 MB of L3 per core, and a much bigger execution window that should finally let AMD's wider design shine. AMD focused on sharing the server details, but we'll do our best to translate this to Ryzen and gaming, too.
via TechPowerUp
AMD has pulled back the curtain on its Zen 6 microarchitecture. We deep-dive into the differences between Zen 5 and 6, as well as detail our first benchmarks of AMD’s Venice CPUs.
via Tom’s Hardware